1. Field of the Invention
The present invention relates to a random access semiconductor memory device including a spare memory cell array besides a main memory cell array.
2. Description of Related Art
In a random access memory (RAM), data can be written and read out at all times. In RAM, as a memory capacity is increased, a redundancy function is often added for the purpose of saving a defective memory cell or defective word line. This redundancy function will be described below. That is, a memory cell having the same arrangement as that of a memory cell in a main memory cell array is arranged in a spare memory cell array in units of word lines. When a memory cell or word line in the main memory cell array is determined to be defective, memory cells of one row including the defective memory cell or memory cells of one row connected to the defective word line are replaced with spare memory cells of one row in the spare memory cell array, so that a product yield can be improved.
As described above, in order to switch from the main memory cell array to the spare memory cell array, a programmable circuit element such as a fuse element is arranged in a main row decoder for driving a word line in the main memory cell array.
FIG. 1 is a circuit diagram showing a part of a circuit associated with one word line of the main row decoder in a conventional semiconductor memory device. Referring to FIG. 1, reference numeral 71 denotes a NAND gate for receiving row address signals output from an address buffer (not shown). An output from the NAND gate 71 is input to an inverter 72 serving as a word line drive circuit. An output from the inverter 72 is output to a corresponding word line 74 through a fuse element 73 of, e.g., polysilicon. A plurality of memory cells 75 are connected to the word line 74 in parallel with each other (note that only one memory cell is shown in FIG. 1). The capacitance of the word line 74 itself and a parasitic capacitance 76 of the plurality of memory cells connected to the word line 74 are equivalently connected between the word line 74 and the ground potential. Note that reference numerals 77 and 78 denote bit lines for receiving complementary data read out from or to be written in each memory cell 75.
In the circuit having the above arrangement, if the word line 74 to which an output from the inverter 72 is applied, or each memory cell 75 connected to the word line 74 is not defective, the above-mentioned fuse element 73 is left in a state immediately after it is manufactured and is not disconnected. In this state, row address signals output from the address buffer are supplied to the NAND gate 71. When an output from the NAND gate 71 is set at "L", an output from the inverter 72 is set at "H", and a corresponding word line 74 is selected and driven.
On the other hand, if the word line 74 is defective, or at least one defective memory cell is present in the plurality of memory cells 75 connected to the word line 74, an energy beam such as a laser light beam is radiated on the fuse element 73, and the fuse element 73 is disconnected. Assume that when the fuse element 73 is disconnected, row address signals are supplied to the NAND gate 71, and an output from the NAND gate 71 is set at "L". However, since the fuse element 73 is disconnected, an output from the NAND gate 71 is not supplied to the inverter 72. Therefore, the word line 74 is not selected nor driven. On the other hand, the row address signals are supplied to the NAND gate 71, so that a spare word line to which memory cells of one row in the spare memory cell array (not shown) are connected is selected and driven by a spare row decoder (not shown). Thus, a defective memory cell in the main memory cell array is replaced by a memory cell in the spare memory cell.
The above-mentioned fuse element 73 of polysilicon has a certain resistance component. As described above, the parasitic capacitance 76 is present on the word line 74. The capacitance 76 tends to be increased as the capacity of the memory device is increased. For this reason, in the conventional semiconductor memory device, an integrated circuit comprises a resistance component of the fuse element 73 and the parasitic capacitance 76, and a time constant of the integrated circuit is increased. Therefore, an output signal of the inverter 72 is considerably delayed. As a result, in the conventional device, high-speed operation cannot be easily realized.
In addition, conventionally, when the fuse element 73 is disconnected, the word line 74 is set in a potential floating state. Therefore, a change in ground potential tends to affect the word line 74, and a stable operation cannot be expected.